1. Field of the Invention
The present invention relates to a delay circuit for delaying an input signal for a desired period, a timing generator for generating a desired timing and a testing apparatus for testing an electronic device. Particularly, the present invention relates to a delay circuit with a small circuit in which the amount of variable delay is small and a linearizing memory is not required. The present application relates to and claims priority from a Japanese Patent Application No. 2003-421617 filed in Japan on Dec. 18, 2003, the contents of which are incorporated herein by reference for all purpose if applicable in the designated state.
2. Related Art
Conventionally, a testing apparatus for testing an electronic device such as a semiconductor device provides a signal to the semiconductor device at a desired timing. For example, the testing apparatus includes a timing generator for generating a timing signal to define the timing.
FIG. 11 shows an example of a configuration of a timing generator included in the conventional testing apparatus. The timing generator 300 includes a counter 310, a timing memory 312, an exclusive OR circuit 314, an AND circuit 316, a linearizing memory 318 and a variable delay circuit 320.
The counter 310, the exclusive OR circuit 314 and the AND circuit 316 generate a delay being an integral multiple of a received reference clock (Ref Clk). That is to say, the counter 310 receives the Ref Clk and outputs the value obtained by counting the pulse number of the Ref Clk. The timing memory 312 receives a timing set signal TS indicative of the timing of a timing signal which should be generated by the timing generator 300 and outputs a control signal dependent on the high-order bit of the timing set signal to the exclusive OR circuit 314.
For example, the timing set signal may be data indicative of the amount of delay for delaying the Ref Clk. The timing memory 312 outputs a quotient obtained by dividing the amount of delay by the cycle of the Ref Clk to the exclusive OR circuit 314. When the counted value provided from the counter 310 is corresponded to the value provided from the timing memory 312, the exclusive OR circuit 314 outputs ‘H’ logic signal. Then, the AND circuit 316 outputs a logical product of the signal received from the exclusive OR circuit 314 and the Ref Clk.
The timing memory 312 outputs a control signal dependent on the low-order bit of a timing set signal to the linearizing memory 318. For example, the timing memory 312 provides delay setting data corresponding to a remainder obtained by dividing the amount of delay indicated by the timing signal by the cycle of the Ref Clk to the linearizing memory 318.
The linearizing memory 318 controls the amount of delay in the variable delay circuit 320 based on the received delay setting data. The variable delay circuit 320 delays the signal outputted from the AND circuit 316 and externally outputs the delayed signal as a timing signal.
The linearizing memory 318 stores control data corresponding to a linearization of the delay setting data in a micro-variable delay circuit 320.
FIG. 12 shows a configuration of the conventional variable delay circuit 320. The variable delay circuit 320 includes a plurality of buffers 324, a multiplexer 322 and a micro-delay section 330. The plurality of buffers 324 are connected in series and delays sequentially the signals outputted from the AND circuit 316. The multiplexer 322 selects the signal outputted from any of the buffers 324 based on the control data received from the linearizing memory 318 and outputs the same to the micro-delay section 330. Thereby the variable delay circuit 320 generates a delay being the integral multiple of the amount of delay in the buffer 324.
The micro-delay section 330 generates a delay of which delay step is less than that in the buffer 324 and of which maximum delay is approximately equal to the delay for one step of the buffer 324. At this time, it is preferred that the amount of maximum delay of the micro-delay section 330 is designed redundantly for the delay for one step of the buffer 324 in order to absorb such as production tolerance. The micro-delay section 330 may include a buffer 326 and a variable capacity 328 and generates a desired micro-delay by changing the capacity of the variable capacity according to the control data.
The delay time in the conventional delay section 330 is defined based on a current to charge/discharge the variable capacity 328 by the buffer 326 and the capacity of the variable capacity 328. Here, the charge/discharge current and the capacity are fluctuated due to process tolerance and the fluctuation of voltage and temperature. Therefore, any error of the amount of delay is generated in the micro-delay section 330.
FIG. 13 shows the amount of delay in the micro-delay section 330 for the control data provided from the linearizing memory 318 to the micro-delay section 330. Thereby the amount of delay in the micro-delay section 330 is fluctuated by 0.6-1.5 times as large as the typical value. In this case, the ratio between the maximum value and the minimum value of the fluctuation of the amount of delay becomes about 2-3 times and it is unable to disregard to fluctuation of the amount of delay.
As for the fluctuation of the amount of delay, the amount of delay in the micro-delay section 330 is actually measured for each value of the process, the voltage and the temperature and stores the delay setting data and the control data in the linearizing memory 318 in association with each other such that the delay setting data provided to the linearizing memory 318 and the actual amount of delay is equal. However, the bit number of the control data stored in the linearizing memory 318 is increased by several bit than the delay setting data because the ratio between the maximum value and the minimum value of the fluctuation of the amount of delay is about 2-3 times as described above. Therefore, the linearizing memory 318 needs to store more data to compensate to the fluctuation of the process tolerance, the voltage and the temperature.
For example, when a period of Ref Clk is 4nS, and a delay resolution in the micro-delay section 330 is 0.98 ps (=4nS/2^12), the address of the linearizing memory 318 is 12 bit (4096 word) while the bit number of the control data is increased to about 15 bit in order to compensate the fluctuation. That is to say, the linearizing memory 318 needs a storage area about 4096w×15 bit and occupies a majority of the circuit in the timing generator 300.
Thus, an object of the present invention is to provide a delay circuit and a testing apparatus being capable of solving the problem accompanying the conventional art. This object is achieved by combining the features recited in independent claims. Then, dependent claims define further effective specific example of the present invention.